研究领域：
碳纳米管集成电路、三维集成电路
基于先进半导体工艺的DTCO/STCO以及大规模数字芯片设计
教育经历：
2012-2017 清华大学工程物理系 博士
2014.11-2015.11 美国范德堡大学电子工程系 联合培养博士生
2008-2012 清华大学工程物理系 本科
工作履历/科研教育经历：
2023/07 - 至今 北京大学电子学院，助理教授
2019/04 - 2023/06 欧洲微电子研究中心（IMEC），长聘高级研究员
2017/09 - 2019/03 法国国家科学院LIRMM实验室，博士后
自我介绍：
主要研究领域是碳纳米管集成电路、三维集成电路、基于先进半导体工艺的DTCO/STCO以及大规模数字芯片设计。累计发表国际期刊和会议论文近60多篇，包括Nature Electronics、IEEE系列等期刊，以及IEDM/VLSI/ISSCC微电子和集成电路三大顶级会议。研究成果受到斯坦福大学、台积电、英特尔、谷歌、高通和华为等顶级大学和半导体公司关注并受邀作报告，研究工作多次获得欧洲微电子研究中心、欧洲主流科技媒体和IEEE Spectrum杂志的亮点报道和采访。主持VLSI 2021三维集成技术研讨会 、召集VLSI 2023芯片背部互连技术研讨会，担任Nature Electronics期刊审稿人和受邀评论人。曾获国家海外高层次青年人才项目、欧盟玛丽居里资助项目（全球工程类申请者排名7/1000）、VLSI 2022大会技术亮点文章、2015-2017年度中国辐射物理领域十大创新科技（基于博士课题）、清华大学优秀博士学位论文等荣誉。
重要研究成果：
期刊文章
[J10] R. Chen*. “Pushing carbon nanotube circuits below the 10-nm node,” Nature Electronics, 473–474 (2023). https://doi.org/10.1038/s41928-023-00986-0
[J09] R. Chen*, et al., “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances—Part I: Pristine MWCNT,” IEEE Transactions on Electron Devices, Vol. 65, No. 11, pp. 4955-4962, Nov. 2018.
[J08] R. Chen*, et al., “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances—Part II: Impact of Charge Transfer Doping,” IEEE Transactions on Electron Devices, Vol. 65, No. 11, pp. 4963-4970, Nov. 2018.
[J07] R. Chen*, et al., “Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation-Part I: CNFET transistor optimization,” IEEE Transactions on VLSI Systems, Vol. 30, No. 4, pp. 432-439, Feb. 2022; DOI: 10.1109/TVLSI.2022.3146125
[J06] R. Chen*, et al., “Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation-Part II: CNT interconnect optimization,” IEEE Transactions on VLSI Systems, Vol. 30, No. 4, pp. 440-448, Feb. 2022; DOI: 10.1109/TVLSI.2022.3146064
[J05] R. Chen*, et al., “Effects of total-ionizing-dose irradiation on SEU- and SET-induced soft errors in bulk 40-nm sequential circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 1, pp. 471-476, January 2017.
[J04] R. Chen*, et al., “Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 8, pp. 2122-2128, Aug. 2017.
[J03] R. Chen*, et al., “Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 8, pp. 2098-2106, Aug. 2017.
[J02] R. Chen*, et al., “Single-event multiple transients in conventional and guard-ring hardened inverter chains under pulsed-laser and heavy ion irradiation,” IEEE Transactions on Nuclear Science, Vol. 64, No. 9, pp. 2511-2518, Sep. 2017.
[J01] R. Chen*, et al., “Analysis of Temporal Masking Effects in Master and Slave Type Flip-Flop SEUs and Related Applications,” IEEE Transactions on Nuclear Science, Vol. 65, No. 8, pp. 1823-1829, Aug. 2018.
会议文章
[C05] R. Chen, et al., “Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node,” 2022 Symposium on VLSI Technology and Circuits, June, Hawaii, USA. (国际超大规模集成电路会议，论文入选大会Technology Focus Session (总共9篇)，同年另有一篇共同作者论文入选大会Highlight Session (总共5篇))
[C04] R. Chen, et al., “Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network,” 2022 IEDM. (国际电子器件大会，接受特邀报道：IEEE Spectrum: https://spectrum.ieee.org/interconnect-back-side-power)
[C03] R. Chen, et al., “Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node,” 2021 IEDM. (国际电子器件大会， imec亮点介绍，欧洲半导体媒体eeNews, SILICON semiconductor等重点报道)
[C02] R. Chen, et al., “3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes,” 2020 IEDM. (国际电子器件大会)
[C01] R. Chen, et al., “Invited Paper: Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection,” 2022 ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP). (邀请报告)
著作
《纳米体硅CMOS工艺逻辑电路单粒子效应研究》，清华大学出版社，2020.11，陈荣梅 著
